1. Field of the Invention
The present invention relates in general to an output driver circuit for integrated circuits and, in particular, to an output driver circuit having a controlled body bias. Still more particularly, the present invention relates to a controlled body bias output driver circuit for use in devices having multiple power supplies.
2. Description of the Prior Art
Semiconductor chips typically contain one or more outputs suitable for connection to off-chip "buses", which allow multiple devices to transfer data on a single line. Most logic gates and integrated circuit devices utilize drivers or buffers at their output when driving signals over long transfer lines such as a communication bus. An output driver is typically comprised of large transistors which are capable of furnishing drive current beyond the capacity of most of the on-chip logic gates. In order to prevent errors in communication on a bus, the chip will control the output drivers connected to the shared bus through a given handshaking protocol and addressing scheme so that only one device is communicating on the bus at any one time. Thus, when used to drive a data bus, output drivers are typically of a 3-state output arrangement. A driver with a three state output behaves like any ordinary pull-up logic driver when enabled, always driving its output either high or low. When disabled, it effectively disconnects, or "open-circuits", its output from the bus so other logic devices can drive the same line.
One traditional output driver is the "CMOS Inverter" output device. This driver comprises a PMOS transistor in series with an NMOS transistor, their gates driven by the same input signal. This driver design has been successful due to its low power consumption and high speed operation. However, under certain operating conditions, this design is susceptible to latch-up. In particular, potential latch-up problems occur when the logic gate or device utilizing the CMOS inverter driver operates in multiple power supply ranges. Multiple power supply and ground pins are commonly provided with integrated circuits to reduce operational effects induced by output noise in high performance applications.
In order to avoid the latch-up problem in a CMOS driver, a stacked NMOS output driver as seen in FIG. 1 could be used. Here, two NMOS transistors are connected in series and are supplied with complementary input signals. This configuration provides a pull-up transistor for sourcing the output up to the high rail in response to a logic high input, and a pull-down transistor for sinking the output low in response to a logic low input. Transistor M1 is biased with V.sub.CCQ, and the gate input is signal N1out. The transistor M1 acts as a source follower to force a high signal output on the driver output DQ when turned on. Transistor M2 is placed in series with transistor M1. The input at the gate of transistor M2 is signal N0out which is the complement to N1out. Thus, in operation, when signal N1out is high, transistor M1 is turned on and transistor M2 is turned off. This sources the driver output DQ to a voltage of approximately V.sub.CCQ. When the driver input N C1out is low, the complementary signal N0out is high. Transistor M1 is switched off and transistor M2 is switched on. This pushes the driver output DQ down to the lower rail voltage attached to the source of transistor M2, in this case ground. Because transistor M1 pulls the output high and transistor M2 pushes the output low, this type of output driver has been called a "push-pull" configuration. In the disabled state, both N1out and N0out are low, turning M1 and M2 off to effectively open circuit the connection to the output.
In a typical design for the stacked NMOS driver, the P-well of both transistors would be grounded. However, for the pull-up MOSFET, any change in the driver output voltage produces a source-substrate voltage. This in turn results in a higher threshold voltage through the body effect, resulting in a reduced switching speed. The body effect is due to the influence of the substrate acting as a second gate. This degrades performance by changing the point at which the transistor turns on, thereby slowing its switching speed. In order to avoid the body effect, the source-substrate voltage must remain at zero.
In the FIG. 1 design, both transistors have their substrate tied to their source to avoid the body effect. With this design, variations in switching speed caused by source-substrate voltage does not occur. Although this design significantly improves the slew rate of transistor M1 when turned on, having the output tied to the substrate or well-tie of transistor M1 slows the rate at which transistor M1 turns off when a low signal is placed on N1out.
Moreover, when the driver is used by a device capable of being referenced to multiple power supplies, there is a significant potential for latch-up of the driver coming from the output-tied well of transistor M1. Latching occurs when the driver is referenced to an upper rail voltage lower than the substrate voltage. This causes the inherent P-well to bulk silicon PN junction to become forward biased. With an NMOS transistor adjacent to this junction, a severe latch-up mechanism will be initiated by the PNPN structure. Such a latch-up renders the device non-operational. The negative voltage differential between the drain and substrate may occur from a transient on the output pin or an output signal from another device referenced to a higher voltage.
Therefore, it would be desirable to have a stacked NMOS output driver having an increased driver switching speed and is less susceptible to latch-up while operating in a tri-state mode on a device having multiple power supply pins.